The present disclosure relates to predicting the laminate substrate warpage. More particularly, the present disclosure relates to analyzing conductive layers included in the laminate substrate and adjusting the composition of the conductive layers so that the warpage is minimized.
Laminate substrates are designed for electrical functionality and typically include a glass fiber reinforced core; “top” and “bottom” conductive layers; and top/bottom dielectric layers that are placed between the conductive layers. The conductive layers include a conductive material (e.g., copper) that is circuitized during fabrication according to each layer's corresponding design. The top and bottom conductive layers are typically utilized for signal routing (wiring layers) and as power layers (voltage and ground).
Laminate warpage results when a different bending resistance and/or bending forces exist above and below the laminate substrate's core. A coefficient of thermal expansion (CTE) mismatch between the dielectric layers and the copper remaining on the conductive layers and dielectric cure shrinkage during fabrication are driving forces for bending as the temperature changes, such as during module assembly operations or during laminate fabrication.
Current industry practice is to reduce laminate warpage at the design stage by using one of the following methods. a) Reducing out-of-plane copper imbalance, b) using analytical equations based on classical laminate plate theory, however, analytical equations are not exact but only an approximation, and prone to error due to volume averaging and material property assumptions made, c) performing Finite-Element based mechanical modeling to predict warpage, which is time consuming and prone to error due to material property assumptions made in the model.